It is necessary to accurately measure load current in order to accomplish control of a variety of devices including electric current motors, DC-DC converter circuits and voltage regulator circuits. A known circuit 100 for measuring load current via inductor current flow in a DC-DC converter is shown in FIG. 1(a). The portion of circuit 100 to the right of the vertical dashed line between pins ISENSE− and ISENSE+ is typically internal to the IC chip, while the portion including the low pass filter comprising inductor L 110 and CFILTER (output capacitor) that is typically external to the IC chip is to the left of the dashed line between ISENSE− and ISENSE+. External inductor L 110, with an inductance of L having DC resistance DCR, forms part of the low pass filter network with CFILTER that turns an applied pulse width modulated input signal, provided by a pulse width modulator (PWM; not shown) into a steady state voltage output, VOUT, across a load RLOAD. A portion of the voltage drop across L 110 is due to its DC resistance, shown as DCR. A resistor in series with a capacitor, RIND and CIND, is shown placed across inductor 110, RIND/CIND providing a time constant that closely matches the time constant of L/DCR.
The voltage across CIND, shown in FIG. 1(a) as VIND, matches the voltage drop across DCR, and is thus a good indication of inductor current, IIND. An operational amplifier, A1, is placed in circuit 100 to drive the gate of an Nmos transistor, Q1, whose source connects back to the inverting input of A1 at pin ISENSE+. A sense resistor, RSENSE 120, is placed between pin ISENSE+ and VOUT.
A1's non-inverting input, connected to pin ISENSE−, is connected to the junction between RIND and CIND. In this configuration the high gain of A1 drives the voltage at pin ISENSE+ to essentially equal the voltage at pin ISENSE−, so that the voltage across capacitor CIND equal to VIND will be placed across RSENSE. Q1 will then carry a current equal to VIND/RSENSE, or IIND*DCR/RSENSE. This current, ISENSE, is available at the Q1's Drain, IOUT, and can then be processed and used for, among other things, over current trip or setting a regulated output impedance.
Although Q1 is shown in FIG. 1 as being an Nmos transistor, in an alternate embodiment it could also be a combination of Nmos and Pmos, with the drain currents combined to form bidirectional current sensing. It could also be only an Nmos or Pmos, with offset current added at ISENSE+ and subtracted back out at IOUT to allow bidirectional current sensing.
The RSENSE resistor and ISENSE− pin can also be connected across a synchronous rectifier FET. In that case the RDSON of the FET would be the current sensing element instead of the inductor DCR. Load current sensing by sampling the voltage across the lower MOSFET rDS(ON) when the PWM drives a synchronous rectifier is demonstrated in circuit 140 shown in FIG. 1(b). The PWM 150 drives a gate driver 152 which drives the upper and lower (synchronous rectifier) Nmos FET's 156 and 157, which in turn drive inductor 160. The amplifier A1 is ground-reference by connecting the ISEN− input to the source of the MOSFET 157. The inductor current IL flows from Vin through the FET 156 while FET 156 is on, and flows from ground while the lower FET 157 is on. The inductor current (IL) therefore causes a voltage drop across FET 157 equal to the product of RDSon and the inductor current, which is related to the resistance of sense resistor 170 multiplied by the current sensed (ISEN). Specifically, the resulting current into the ISEN+ pin is proportional to the channel current IL. The ISEN current is then sampled and held after sufficient settling time as known in the art. The sampled current can be used for applications including channel-current balance, load-line regulation, and overcurrent protection.
RSENSE in Circuits 100 and 140 is placed off-chip because RSENSE needs to be adjustable, such as to get the desired value of IOUT for circuit 100 for different combinations of DCR and IIND. For instance, if IOUT is compared to a fixed value of current inside an integrated circuit (IC) to generate an over current trip, and the inductor DCR and desired IIND current trip point are set by system constraints, then the value of RSENSE must be adjusted to achieve the desired IOUT at the desired IIND. For the reason of required adjustability, RSENSE is therefore generally placed external to the IC as shown in FIG. 1. A second reason that RSENSE is usually placed external to the IC is that most integrated circuit processes do not support an accurate and stable, internal resistor.
A problem with an external RSENSE is the susceptibility of the ISENSE+ pin to noise pickup indicated in FIGS. 1(a) and 1(b) as noise coupling through parasitic capacitor 130. Referring again to FIG. 1(a), noise current that is capacitively coupled to pin ISENSE+ appears as the drain current of Q1 including a noise component shown in FIG. 1 as IOUT+Noise. Such noise coupling is known to adversely impact performance and has required very careful printed circuit board layouts to minimize the capacitive coupling at pin ISENSE+. It is not generally feasible to try to bypass ISENSE+, as this would put a pole in the feedback of amplifier A1, possibly making A1 unstable.
Thus, there is a need for an improved switching regulator circuit, and specifically for a current measurement circuit which can be used for precisely measuring load current in a switching regulator circuit, motor controller circuit, or the like, that does not require an external, precise RSENSE at the inverting input of A1 with its attendant noise susceptibility.